Logic Gate Circuit Simulator

The assignment: read a circuit netlist and a vector file of input changes over time, then simulate the circuit and produce a waveform. It required three classes — Wire, Gate, and Event — where each Event represents one wire settling on a value at a specific time, processed in order instead of recalculating the whole circuit every step.

The flip-flop's two NOR gates are cross-coupled, which broke our first version — evaluating one gate needed the other's value, and vice versa, with no stable starting point. The fix: a defaulted parameter on evaluate() to test a hypothetical value without committing it, plus a new DEFAULTED wire state to mark it as not yet real.

We tested against every circuit file the course provided, diffing our output against known-correct solutions — most bugs were in event handling. The simulator has real limits: length is capped so a feedback loop can't run forever, and the file format is rigid.